A mobile terminal product such as a mobile phone, a portable instrument or a notebook computer needs to use a dedicated power supply management and control chip to manage charging and discharging of a battery of the device. In consideration of efficiency, heat dissipation and the like, such a power supply management chip gradually tends to use a switch mode with a higher conversion efficiency, and needs to operate at a high voltage (input by an AC adapter); therefore, a DC-DC switch converter that can operate at a high input power supply voltage generally needs to be integrated in the chip. Design, especially a power output level of such a converter, varies greatly with different processes. For a process supporting a high voltage, a power level of a DC-DC converter may be implemented by using a conventional architecture of High Side PMOS+Low Side NMOS shown in FIG. 1. However, the use of the High Side PMOS architecture places a requirement for a PMOS process. For different application scenarios, a higher withstand voltage of a required component needs a longer channel of the PMOS and greater conductive impedance, which is a great challenge for reducing a chip area and improving system efficiency. Theoretically, compared with a PMOS, an NMOS of a same size has lower conductive impedance. To reduce an area of a power tube, a solution in which the PMOS is replaced with the NMOS may be used, that is, a full NMOS (High Side NMOS+Low Side NMOS) architecture shown in FIG. 2. A key of this architecture is to generate a voltage which can make the High Side NMOS conducted, that is, a PVDD+AVDD voltage in phase2 in FIG. 2 for a currently commonly used LDNMOS component. It is known that the PVDD is already a maximum voltage in a circuit. Therefore, a bootstrap (Bootstrap) circuit needs to be used to implement that a conduction voltage of the High Side NMOS reaches the PVDD+AVDD.
In the prior art, an on-chip or off-chip Schottky (Schottky) diode is generally used to implement the Bootstrap circuit. Moreover, as shown in FIG. 2, in phase1, the AVDD directly charges a capacitor CBST by using the Schottky diode. However, in consideration of a factor such as a forward conduction voltage drop (about 0.3 to 0.7 V) of the Schottky diode, a voltage of a BST node cannot be charged to reach the AVDD; therefore, in phase2, because of the charge continuity of the capacitor, the voltage of the BST node may rise to PVDD+AVDD—forward conduction voltage drop (0.3 to 0.7 V), and therefore, it may cause that the High Side NMOS cannot be completely conducted. Therefore, a minimum working voltage further needs to be provided for the circuit to offset the forward conduction voltage drop of the schottky diode. In addition, reverse leakage of the schottky diode is large, which may degrade circuit performance. Moreover, if a BST circuit with an on-chip schottky diode is used, a Schottky process is additionally introduced to a semiconductor manufacturing process, which increases process steps, a production period and cost correspondingly, and limits a range of optional processes as well; and if the off-chip schottky diode is used, an area of a PCB board may be increased, and cost is also increased.